Preliminary Specifications: Programmed Data Processor Model Three (PDP-3) October, 1960 by Digital Equipment Corporation (reading like a writer .TXT) 📕

The Memory Buffer is the central switching register. The word coming from or going to memory is retained in this register. In arithmetic operations it holds the addend, subtrahend, multiplicand, or divisor. The left 6 bits of this register communicate with the Instruction Register. The address portion of the Memory Buffer Register communicates with the Index Adder, the Memory Address Register, and the Program Counter. In certain instructions, the address portion of the control word does not refer to memory but specifies variations of an instruction, thus, the address portion of the Memory Buffer is connected to the Control Element.

The Accumulator is the main register of the Arithmetic Element. Sums and differences are formed in the Accumulator. At the completion of multiplication it holds the high order digits of the product. In division it initially contains the high order digits of the dividend and is left with the remainder.

The logical functions AND, inclusive OR, and exclusive OR, are formed in the Accumulator.

The Carry Storage Register facilitates high-speed multiply and is properly part of the Accumulator.

The In-Out Register is the main path of communication with external equipment. It is also part of the Arithmetic Element. In multiplication it ends with the low order digits of the product. In division it starts with the low order parts of the dividend and ends with the quotient.

The In-Out Register has a full set of shifting properties, (arithmetic and logical).

There are three registers of 15 bit length which deal exclusively with addresses. The design allows for expansion to 18 bits. These registers are:

The Memory Address Register holds the number of the memory location that is currently being interrogated. It receives this number from the Program Counter, the Index Adder or the Memory Buffer.

The Program Counter holds the memory location of the next instruction to be executed.

The Index Adder is a 15 bit ring accumulator. The sum of an instruction base address, Y, and the contents of an index register, C(x), are formed in this register. This register holds the previous content of the Program Counter in the "jump and save Program Counter," jps, instruction. The Index Adder also serves as the step counter in shift, multiply, and divide.

The Control Element contains two six bit registers and several miscellaneous flip-flops. The latter deal with indexing, indirect addressing, memory control, etc. The six bit registers are:

The Instruction Register receives the first six bits of the Memory Buffer Register during the cycle which obtains the instruction from memory (cycle zero). This information is the primary input to the Control Element.

The six Program Flags act as convenient program switches. They are used to indicate separate states of a program. The program can set, clear, or sense the individual flip-flops. The program can also sense or make the state "All Flags ZERO." They can also be used to synchronize various input devices which occur at random times (see Input-Output, Typewriter Input).

Three toggle switch registers are connected to the Central Processor (see Manual Controls).

The fifteen Test Address Switches are used to indicate start points and to select memory registers for manual examination or change.

The thirty-six Test Word Switches indicate a new number for manual deposit into memory. They may also be used for insertion of constants while a program is operating by means of the operate instruction.

The six Sense Switches allow the operator to manually select program options or cause a jump to another program in memory. The program can sense individual switches or the state "All Switches ZERO."

The PDP-3 circuitry is the static type using saturating transistor flip-flops and, for the most part, transistor switch elements. The primary active elements are Micro-Alloy and Micro-Alloy-Diffused transistors. The flip-flops have built-in delay so that a logic net may be sampled and changed simultaneously.

Machine timing is performed by a delay line chain. Auxiliary delay line chains time the step counter instructions (multiply, divide, etc.). The machine is thus internally synchronous with step counter instructions being asynchronous. The machine is asynchronous for in-out operations, that is, the completion of an in-out operation initiates the following instruction.

The PDP-3 consists of two mechanical assemblies, the Console and the Equipment Frame. Fig. 3 is a photograph of PDP-1 which is an 18 bit version of PDP-3.